Citazione: V. Di Lecce, B. Castagnolo, F. Corsi, P.Larizza, D. Lunanuova, A 2-D fft processor in 4um Cmos technology, Melecon '87 e 34' Congress on Elettronics, Rome, pp. 385-388, March 24-26, 1987.
Abstract: A 2D-FFT processor developed for the use in an echographic equipament is described. A SIMD architecture has been employed. constituted by 512 processing elements (PE's) for a 1024x1024 image, interconnetted by a Perfect Shuffle network. Each PE is composed of four floating-point multiplier-adder sections. The IC have been designed for a CMOS implementation of 3 um